In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller feature sizes are required. This includes the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges, of various features. The dimensions of and between such small features can be referred to as critical dimensions. With an ever increasing number of integrated circuit features being formed on a circuit die, the importance of properly designing patterns to form structures that are isolated and non-interfering with one another has also increased.
The requirement of small features with close spacing between adjacent features requires high resolution lithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon structure is coated uniformly with a radiation-sensitive film (a resist or a lithographic coating) and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the coated silicon structure through an intervening master template. The intervening master template is generally known as a mask, photomask, or reticle for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative image or a positive image of the subject pattern. Exposure of the coating through a reticle, mask or photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The process of manufacturing semiconductors (e.g., integrated circuits, ICs, chips) employing masks typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Generally, the process involves creating several patterned layers on and into the substrate that ultimately forms the complete integrated circuit. The patterned layers are created, in part, by the light that passes through the masks. A series of lenses provides for reduction in size from the mask to the projected image onto the resist. The optical equipment for traditional photolithographic processes requires significant capital investment.
Nanoprint (also know as nanoprint lithography, imprint lithography, nanoimprint or nanoimprint lithography) technologies are emerging which provide an alternative in which the capital investment is significantly reduced in part because patterns are exposed through a 1:1 mask in close proximity to the wafer. Imprint lithography is relatively inexpensive because it avoids costly optics, as well as cumbersome enhancement techniques like phase-shift masks. Capital cost for equipment is far less than typical step-and-scan or scan and repeat systems. Imprint lithography does not depend on optical elements; rather, the line width is determined solely by the mask or mold.
In a conventional nanoprint process a UV-transmittable quartz mask/mold is pressed into a thin film of low viscosity UV-curable monomer coated onto a substrate. Subsequent exposure of the substrate by UV-irradiation through the mask/mold results in polymerization and curing of the resist in the imprinted area. Thereafter the mold is removed leaving an inverted three-dimensional replica of its pattern into the cured imprint polymer. Finally, the residual imprint layer in the depressed areas is removed by high anisotropic reactive ion etching. One advantage is that the circuit designers do not need to be concerned about optical proximity correction which otherwise limits how patterns are placed on the mask. Furthermore, patterning on top of a grating or other surfaces with severe topological features is possible providing significant advantages in MEMS applications.
Because nanoprint lithographic methods do not utilize the typical 4× optical reduction employed in conventional lithographic processes, the small feature sizes are more difficult to achieve. In order to produce devices with similar critical dimensions to conventional optical lithographic methods, new processes and techniques are required.